Pin-out and Electrical Details
The following section describes the pin-out, pin descriptions and electrical details related to the PQ60 standard.
Pin-out with Pin Descriptions
This section provides the pin-out and electrical details of the connector used. Each signal on the connector is discussed. The relevant information can be found in Figure 4.1 and Table 4.1.
| +3.3_Sw1 | P1 | P60 | 3V3 bus |
| +3.3_Sw1 | P2 | P59 | 3V3 bus |
| RTN_SW1_3V3 | P3 | P58 | 3V3 bus |
| RTN_SW1_3V3 | P4 | P57 | 3V3 bus |
| +3.3_Sw2 | P5 | P56 | RTN_3V3 |
| +3.3_Sw2 | P6 | P55 | RTN_3V3 |
| RTN_SW2_3V3 | P7 | P54 | RTN_3V3 |
| RTN_SW2_3V3 | P8 | P53 | RTN_3V3 |
| +3.3_Sw3 | P9 | P52 | BatV bus |
| +3.3_Sw3 | P10 | P51 | BatV bus |
| RTN_SW3_3V3 | P11 | P50 | BatV bus |
| RTN_SW3_3V3 | P12 | P49 | BatV bus |
| BatV_SW1 | P13 | P48 | RTN_BatV |
| BatV_SW1 | P14 | P47 | RTN_BatV |
| RTN_SW1_BatV | P15 | P46 | RTN_BatV |
| RTN_SW1_BatV | P16 | P45 | RTN_BatV |
| BatV_SW2 | P17 | P44 | GPIO12 |
| BatV_SW2 | P18 | P43 | GPIO11 |
| RTN_SW2_BatV | P19 | P42 | GPIO10 |
| RTN_SW2_BatV | P20 | P41 | GPIO9 |
| BatV_SW3 | P21 | P40 | GPIO8 |
| BatV_SW3 | P22 | P39 | GPIO7 |
| RTN_SW3_BatV | P23 | P38 | GPIO6 |
| RTN_SW3_BatV | P24 | P37 | GPIO5 |
| GPIO0 | P25 | P36 | GPIO4 |
| GPIO1 | P26 | P35 | GPIO3 |
| RST | P27 | P34 | SS/GPIO2 |
| GND | P28 | P33 | SCK |
| SCL | P29 | P32 | MISO |
| SDA | P30 | P31 | MOSI |
| Table 4.1: Detailed information on the pins | |||
|---|---|---|---|
| Pin Number | Name | Function | Current, A |
| 1 + 2 | +3.3_Sw1 | Switch 1 Output | 0.4 (combined) |
| 3 + 4 | RTN_SW1_3V3 | Switch 1 Return | 0.4 (combined) |
| 5 + 6 | +3.3_Sw2 | Switch 2 Output | 0.4 (combined) |
| 7 + 8 | RTN_SW2_3V3 | Switch 2 Return | 0.4 (combined) |
| 9 + 10 | +3.3_Sw3 | Switch 3 Output | 0.4 (combined) |
| 11 + 12 | RTN_SW3_3V3 | Switch 3 Return | 0.4 (combined) |
| 13 + 14 | BatV_Sw1 | BatV Switch 1 Output | 0.4 (combined) |
| 15 + 16 | RTN_SW1_BatV | BatV Switch 1 Return | 0.4 (combined) |
| 17 + 18 | BatV_Sw2 | BatV Switch 2 Output | 0.4 (combined) |
| 19 + 20 | RTN_SW2_BatV | BatV Switch 2 Return | 0.4 (combined) |
| 21 + 22 | BatV_Sw3 | BatV Switch 3 Output | 0.4 (combined) |
| 23 + 24 | RTN_SW3_BatV | BatV Switch 3 Return | 0.4 (combined) |
| 25 | GPIO0 | General I/O | 0.2 |
| 26 | GPIO1 | General I/O | 0.2 |
| 27 | RST | Master Reset Line | 0.2 |
| 28 | GND | System Ground | 0.2 |
| 29 | SCL | I²C Clock Line | 0.2 |
| 30 | SDA | I²C Data Line | 0.2 |
| 31 | MOSI | SPI MOSI | 0.2 |
| 32 | MISO | SPI MISO | 0.2 |
| 33 | SCK | SPI Clock | 0.2 |
| 34 | SS / GPIO2 | Slave Select / General I/O | 0.2 |
| 35 | GPIO3 | General I/O | 0.2 |
| 36 | GPIO4 | General I/O | 0.2 |
| 37 | GPIO5 | General I/O | 0.2 |
| 38 | GPIO6 | General I/O | 0.2 |
| 39 | GPIO7 | General I/O | 0.2 |
| 40 | GPIO8 | General I/O | 0.2 |
| 41 | GPIO9 | General I/O | 0.2 |
| 42 | GPIO10 | General I/O | 0.2 |
| 43 | GPIO11 | General I/O | 0.2 |
| 44 | GPIO12 | General I/O | 0.2 |
| 45 - 48 | RTN_BatV | Battery Bus Return | 0.8 (combined) |
| 49 - 52 | BatV bus | Battery Bus | 0.8 (combined) |
| 53 - 56 | RTN_3V3 | 3V3 Bus Return | 0.8 (combined) |
| 57 - 60 | 3V3 bus | 3V3 Bus | 0.8 (combined) |
+3.3V_Sw1-3 / RTN_SW1-3_3V3
These lines are for 3.3V switched power lines. These power lines are designed to be connected to low current systems that are required, or desired, to be switched on and off by the user. It is envisioned that these lines will originate from either a power system or a power distribution board.
BatV_Sw1-3 / RTN_SW1-3_BatV
These lines are for battery voltage switched power lines. These power lines are designed to be connected to low current systems that are required, or desired, to be switched on and off by the user. It is envisioned that these lines will originate from either a power system or a power distribution board.
GPIO 0,1,3-12
These lines are provided to the user for general use. Some examples would be: discrete line control, additional communication lines, analogue lines or any other signal relevant to the system under design.
RST / GND
A dedicated line present on every board on the stack, the RST line, with an associated GND signal, can be used as a master reset line for all systems connected to the stack.
SCL / SDA
An I2C data bus is provided on these lines.
MOSI, MISO, SCK
These lines provide a SPI bus.
SS / GPIO2
This pin provides either a dedicated SS line for the SPI bus or an additional GPIO line.
BatV Bus / RTN_BatV
A battery bus and return line. This is to be a protected bus, designed to power systems within the PQ. This line will be provided by a power system or power distribution board.
This line should not be used as an unprotected battery bus for the main power source of the PQ.
3V3 Bus / RTN_3V3
A 3V3 bus and return line. This bus should be a protected bus, designed to power systems within the PQ. This line will be provided by a power system or power distribution board.
Mounting Holes
The PQ60 standard calls for four mounting holes for each board. Each of these holes should be plated and be connected to chassis ground via the mechanical fixings used between each board. This is not ground as described in the Table 4.1 but the chassis ground of the satellite. The user should only connect to the mounting points if there is a requirement for the chassis ground to be used on the board.
The reason for this requirement is to ensure that all boards used in the stack have a common signal through these points. The approach used should protect the user from ground loops and interfacing issues between different boards.